Overview


Título del trabajo: System And Silicon Debug Engineer

Compañía: Intel

Descripción de funciones: Drives and develops testability and manufacturability of integrated circuits from the component feasibility stage through production ramp. Contributes to design, development, and validation of testability circuits, test flows, and methodologies for new products through evaluation, development, and debug of complex test methods. Interfaces with process development, fab, factory, assembly, quality and reliability, and manufacturing groups to enable postsilicon HVM ramp. Evaluates new designs on automatic test equipment (ATE) and works with the design, DFx, and product development teams to debug functionality and performance issues to root cause. Performs ATE device characterization, utilizes that data to define datasheet specifications and performs yield analysis. Collaborates with designers to drive design for test/debug/manufacturing (DFT/DFD/DFM) features enabling efficient production testing of new products. Develops and debugs complex software programs to convert design validation vectors and drive complex test equipment. Creates and tests validation and production test hardware solutions. Tests, validates, modifies, and redesigns circuits to guarantee component margin to specification. Analyzes and evaluates component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability. Ensures manufacturability over process and product design through thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp. Drives test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations. Analyzes early customer returns with emphasis on driving test hole closure activities. Creates and applies concepts for optimizing component production relative to both quality and cost constraints. Leads and drives manufacturing readiness from fab, assembly, and test factory to support engineering sample and customer sample generation (ES milestones), wafer start planning, product qual execution strategy and capacity analysis, and assembly and test site certification activities. Works with fab, assembly, and test factory partners and planners to support production ramp. May also manage execution of new product introductions in the fab, fab process targeting, product/process optimizations, and participate in factory task forces to bring product perspective and respond to product issues. Optimizes product supply through data analysis of postsilicon binsplit, die level cherry pick (DLCP), and optimize sort/test content and yield downstream through data analysis.**Qualifications**:**Qualifications**:Minimum QualificationsBachelor’s degree in Electrical/Electronics Computer Science, Software Engineer or related field OR related experience in lieu of degree.- Minimum of 3 years’ experience in semiconductor or automation related experience.- Intermediate to advanced English LevelPreferred Qualifications:- Hardware Debug Validation knowledge- Experience on System and Silicon Debug- Data Extraction and Analysis- Experience on Intel IA 32 Architecture- Experience on Xeon Intel Architecture- Scripting in Python, Perl, C or similar- Computer Architecture knowledge**Inside this Business Group**:The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel’s silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel’s brand by providing the infrastructure necessary to enable all of Intel’s products to hit the market on a dependable and predictable cadence.**Posting Statement**:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.**Benefits**:We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.**Working Model**:This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. **In certain circumstances the work model may change to accommodate business needs.**JobTypeHybrid

Ubicación: San José

Fecha del trabajo: Mon, 29 Apr 2024 22:06:49 GMT